1. Field of the Invention
This invention relates to a memory device with an error correction system configured to be 4-bit error correctable.
2. Description of the Related Art
As a memory device is miniaturized and has a great capacity, the data retention characteristic (i.e., data reliability) is reduced. Specifically, in case a multi-level data storage scheme is adapted to the memory device, the data retention property will become a large problem. In a phase change memory and a resistance change memory, which are expected to succeed a conventional NAND-type flash memory, there is such a problem that a data state is not stable, and it is difficult to secure the data retention reliability.
Therefore, it becomes a material technology to form an ECC (Error Correcting Code) system in a memory chip for error-detecting and correcting read data prior to data outputting.
There has already been proposed such a technology that an ECC circuit is built in a flash memory chip or memory controller thereof (for example, JP-A-2000-173289).
If error location search in a BCH-ECC system, which is constituted by use of Galois field (finite field) GF(2n) to perform error-correction for 2-bit or more errors, is performed in such a manner as to substitute elements of the Galois field one by one and select them as solutions satisfying an error location searching equation, thereby searching an error location, the arithmetic operation time will be very long.
Even if the ECC system is formed as on-chip type one, this leads to great reduction of the read/write performance.
Therefore, it is required of us to achieve a high speed ECC system, which does not sacrifice the performance of a conventional flash memory without the above-described one by one searching.